Test and diagnosis of FPGA cluster using partial reconfiguration

FPGA undergoes a large number of test configurations for faults detection and diagnosis which requires a significant amount of test time and off-chip memory to store test configuration bits. Some FPGAs support partial reconfiguration in which a portion of FPGA can be reconfigured without reconfiguring the remaining portions. This partial reconfiguration approach can be utilized for FPGA testing, to reduce the amount of test time and configuration bit storage. In this paper, we propose a Built-In Self-test (BIST) scheme utilizing partial reconfigurability of a mesh FPGA. To implement the BIST scheme, automated tools are developed to produce the required configuration bitstream using standard FPGA CAD flow. A comparative analysis of partial and full reconfiguration is presented which shows that test time and storage size for configuration bitstream reduce to half using partial reconfiguration approach.