Fast register criticality evaluation in a SPARC microprocessor

Many applications impose safety and/or security constraints which require protections against the effects of transient faults. The most critical elements must be identified to achieve good efficiency and cost trade-offs when selective hardening is necessary. In embedded microprocessor-based systems (i.e. most of SoCs) the system dependability is strongly correlated with internal register criticality since external memories are protected by error correcting codes. The robustness analysis of these systems consists in precisely assessing the criticality of internal registers used by the application program. The evaluation often aims at selecting a minimum number of registers to be protected. At the same time, the accurate assessment is complicated in the case of recent processors because of the evolution of architectures and the implementation of new mechanisms to improve performance (e.g, pipeline, forwarding mechanisms,...). Classical fault-injection approaches require long experimental times to determine the most critical set of registers. This paper presents an approach based on modeling the effect of transient faults taking into account the micro-architectural features and proposes a new methodology to refine and accelerate evaluations of register criticality. This new approach is compared with fault injections. The results show the effectiveness of the prediction algorithm.