• DocumentCode
    1777520
  • Title

    Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits

  • Author

    Tenace, Valerio ; Calimera, Andrea ; Macii, Enrico ; Poncino, Massimo

  • Author_Institution
    Dipt. di Autom. e Inf., Politec. di Torino, Turin, Italy
  • fYear
    2014
  • fDate
    June 30 2014-July 3 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this work we quantify the figures of merit of p-n junction based adiabatic graphene circuits implemented through a new logic design style, the Adiabatic Pass-XNOR Logic style (Adiabatic-PXL). First we show how graphene p-n junctions naturally implement transmission gates with embedded XNOR functionality (the Pass-XNOR gate); second, we present a dedicated logic synthesis flow for integrating those gates into adiabatic logic circuits with ultra low-power features. Simulation results have shown that Adiabatic-PXL circuits are 4.2X to 5.5X more energy efficient than non-adiabatic counterparts, still with significant amount of area savings (67% less devices on average).
  • Keywords
    NOR circuits; graphene; logic design; low-power electronics; embedded XNOR functionality; figure-of-merit quantification; graphene-based adiabatic PXL circuits; graphene-based adiabatic pass-XNOR logic circuits; logic design style; logic synthesis flow; p-n junction-based adiabatic graphene circuits; pass-XNOR gate; transmission gates; ultralow-power features; Boolean functions; CMOS integrated circuits; Data structures; Graphene; Logic gates; P-n junctions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Ph.D. Research in Microelectronics and Electronics (PRIME), 2014 10th Conference on
  • Conference_Location
    Grenoble
  • Type

    conf

  • DOI
    10.1109/PRIME.2014.6872678
  • Filename
    6872678