DocumentCode
1777554
Title
Design considerations for monolithically integrated fully-depleted CMOS image sensors
Author
Lincelles, J.B. ; Marcelot, O. ; Magnan, P. ; Saint-Pe, O.
Author_Institution
Integrated Image Sensor Lab., ISAE, Toulouse, France
fYear
2014
fDate
June 30 2014-July 3 2014
Firstpage
1
Lastpage
4
Abstract
We present a design study for the fabrication of a fully depleted CMOS image sensor integrated on high-resistivity epitaxial layer. Both models and simulations are used and show that the maximal depleted thickness and the punch-trough current are dependent on the photo-diode cathode length. From these considerations, achievable performances are estimated.
Keywords
CMOS image sensors; integrated circuit design; integrated circuit modelling; monolithic integrated circuits; photocathodes; photodetectors; photodiodes; semiconductor epitaxial layers; high-resistivity epitaxial layer; maximal depleted thickness; monolithically integrated fully-depleted CMOS image sensor; photodiode cathode length; punch-trough current; CMOS integrated circuits; Cathodes; Data models; Epitaxial growth; Silicon; Three-dimensional displays; CMOS image sensor; fully-depleted; high resistivity silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Ph.D. Research in Microelectronics and Electronics (PRIME), 2014 10th Conference on
Conference_Location
Grenoble
Type
conf
DOI
10.1109/PRIME.2014.6872697
Filename
6872697
Link To Document