Title :
Time interleaved current steering DAC for ultra-high conversion rate
Author :
Da Feng ; Sai-Weng Sin ; Bonizzoni, Edoardo ; Maloberti, Franco
Author_Institution :
State-Key Lab. of Analog & Mixed-Signal VLSI, Univ. of Macau, Macao, China
fDate :
June 30 2014-July 3 2014
Abstract :
A four-path time interleaved current steering DAC is presented. It requires the same number of unity current generators of the plain counterpart, thanks to the use of a digital ΣΔ modulator, thus leading to a lower number of unity current switchings. The benefit is that the non-linearity caused by clock feedthrough is attenuated. Behavioral level simulation results show that the SFDR of a 12-bit DAC operating at 12 GS/s can be 60 dB.
Keywords :
sigma-delta modulation; behavioral level simulation; clock feedthrough; digital ΣΔ modulator; four-path time interleaved current steering DAC; ultra-high conversion rate; unity current generators; unity current switchings; word length 12 bit;
Conference_Titel :
Ph.D. Research in Microelectronics and Electronics (PRIME), 2014 10th Conference on
Conference_Location :
Grenoble
DOI :
10.1109/PRIME.2014.6872724
