Statistical analysis of harmonic distortion in a differential bootstrapped sample and hold circuit

The bootstrap technique is known to increase the linearity of Sample and Hold (S/H) circuit by reducing the input signal dependency of the transistor-switch resistance. But some nonlinearities remain due to parasitic capacitances, mobility degradation and back gate effect resulting in a second order harmonic spurious which can be reduced with a differential architecture. However mismatch between channels limits this technique. In this paper, we provide a general framework to analyze the residual nonlinearity in bootstrapped S/H. Statistical laws are also provided converting harmonic distortion specifications into matching requirements for differential sampling and therefore provide key rules for S/H designers.