High-speed serial interface with a full digital delay-loop

This paper presents a high-speed serial interface with a PLL-less clock and data recovery circuit in 65nm CMOS. A digitally controlled delay line combined with a sample&hold register is used as self-calibrating time-to-digital converter, measuring the phase offset between data and clock. The same line is then utilized to delay the clock appropriately to allow error-free sampling of the data. In contrast to analog DLLs, initial lock can be achieved after transmission of four bits, requiring minimal protocol overhead for synchronization in burst-mode transmissions. The CDR circuit is optimized for 1.228 Gbit/s and consumes 1.9mA from 1.2V supply, with a maximum jitter of 1.8 ps. The overall power consumption is 10.7mW.