Sensitivity based methodologies for process variation aware analog IC optimization

With the continuous downscaling of CMOS technology over the last two decades, reliability of CMOS circuits has become a more critical design issue due to the worsening effects of process variations. Conventionally, variability analysis has been performed following the design process after which the design is modified based on the variation effects, if necessary. However, increased variation and mismatch problems have enforced designers to consider robustness as a design objective that should be maximized. Besides the variability problem, increased non-idealities with more advanced technologies have complicated circuit analysis, and caused unacceptably long design times. Therefore, design automation tools for analog circuits have become crucial to keep the synthesis time within acceptable limits even if variability analysis is included. In this paper, two different methodologies are proposed and discussed for variation aware design automation of analog circuits: Over-Design approach that is based on guard-banding the circuit performance and Variation-Aware Design approach depending on looking for more robust solutions in the dedicated search space. The superiorities of the proposed approaches are discussed via the synthesis results of a two stage OTA example.