Reliability analysis of logic circuits using probabilistic techniques

The low reliability of advanced CMOS devices has become a critical issue that can potentially supersede the benefits of the technology shrinking process. This is making the design time reliability assessment and optimization a mandatory step in the IC design flow. As part of our ongoing research, we describe an algorithm based on probability analysis and logic principles for computing the impact of gate failures on the circuit output. We also propose a Bound and Propagate based methodology to handle the reconvergent fanout issue. A reliability evaluator has been developed around the open source logic synthesis tool `abc´ to allow integration and evaluation of our method in the context of an IC design flow. This approach had tremendously reduced the computation time while maintaining adequate precision. Simulation results for several benchmark circuits demonstrate the accuracy and the simulation time advantages when compared to MonteCarlo simulations.