Structured design to optimize the output power of stacked power amplifiers

Author

Sobotta, Elena ; Wolf, Robert ; Fritsche, David ; Ellinger, Frank

Author_Institution

Circuit Design & Network Theor., Tech. Univ. Dresden, Dresden, Germany

fYear

2014

fDate

June 30 2014-July 3 2014

Firstpage

1

Lastpage

4

Abstract

An enhancement of an analytical algorithm to simplify and structure the design of stacked power amplifiers is presented in this work. This enhancement includes the calculation of passive networks, which compensate the parasitic capacitances of the transistors and thereby increase the distortion-free output power and the power added efficiency (PAE). As an example the algorithm is applied to a power amplifier (PA), using the IBM 180 nm CMOS process. The PA operates at 2GHz for the long term evolution (LTE) standard. The post-layout-simulation exhibits an output power in the 1 dB compression point of 28.2 dBm, leading to a PAE of 30%. The relative 3 dB bandwidth of the output power reaches a high value of 33%. The PA fulfills the specifications of LTE and therewith the high requirements on linearity.

Keywords

CMOS analogue integrated circuits; Long Term Evolution; UHF integrated circuits; UHF power amplifiers; passive networks; IBM CMOS process; LTE standard; PAE; analytical algorithm enhancement; distortion-free output power; frequency 2 GHz; long term evolution standard; parasitic capacitances; passive networks; post-layout-simulation; power added efficiency; size 180 nm; stacked power amplifiers; structured design; Algorithm design and analysis; CMOS integrated circuits; Capacitance; Impedance; Inductors; Power generation; Transistors; CMOS; LTE; load lines; stacked power amplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Ph.D. Research in Microelectronics and Electronics (PRIME), 2014 10th Conference on

Conference_Location

Grenoble

Type

conf

DOI

10.1109/PRIME.2014.6872746

Filename

6872746