Safe operation region characterization for quantifying the reliability of CMOS logic affected by process variations

Author

Khalid, Usman ; Mastrandrea, Antonio ; Olivieri, Mauro

Author_Institution

Dept. of Inf., Electron. & Telecommun. Eng., Sapienza Univ. of Rome, Rome, Italy

fYear

2014

fDate

June 30 2014-July 3 2014

Firstpage

1

Lastpage

4

Abstract

Technology parameter variations combined with voltage noise can become a major cause of logic errors in digital circuits. This presentation brings in the idea of “safe operation region” to permit a robust analytical Monte Carlo evaluation of the reliability of logic circuits in a given technology, avoiding time-consuming SPICE-level or device-level Monte Carlo simulations. The application of the approach is demonstrated for the case of a 22 nm bulk CMOS process.

Keywords

CMOS logic circuits; Monte Carlo methods; integrated circuit noise; integrated circuit reliability; CMOS logic circuit reliability; device-level Monte Carlo simulations; digital circuits; logic errors; process variations; robust analytical Monte Carlo evaluation; safe operation region characterization; size 22 nm; technology parameter variations; time-consuming SPICE-level; voltage noise; Integrated circuit modeling; Inverters; Monte Carlo methods; Noise; SPICE; Standards; Threshold voltage; Failure probability; input-signal variation; nano-CMOS circuits; process variations;

fLanguage

English

Publisher

ieee

Conference_Titel

Ph.D. Research in Microelectronics and Electronics (PRIME), 2014 10th Conference on

Conference_Location

Grenoble

Type

conf

DOI

10.1109/PRIME.2014.6872763

Filename

6872763