Title :
High-speed and pipelined finite field bit-parallel multiplier over GF(2m) for elliptic curve cryptosystems
Author :
Rashidi, Bahram ; Farashahi, Reza Rezaeian ; Sayedi, Sayed Masoud
Author_Institution :
Dept. of Elec. & Comp. Eng., Isfahan Univ. of Technol., Isfahan, Iran
Abstract :
This paper presents a high-speed and pipelined bit-parallel multiplier over binary finite fields for elliptic curve cryptosystems. The architecture of this multiplier is based on a parallel structure and multiplication by 2, so that the two inputs apply to the circuit simultaneously and in parallel form. Furthermore, the structure of the proposed circuit is reconfigurable to the change of the field size. Our implementation is in the gate level by high-speed and low-cost combinational logic circuits. The pipelining technique is applied to the proposed architecture to shorten the critical path delay and to conclude the computations in one clock cycle. The proposed architecture is efficient for FPGA and VLSI implementation. This work has been successfully verified and synthesized using Xilinx ISE 11 by Virtex-4, XC4VLX200 FPGA.
Keywords :
clocks; combinational circuits; field programmable gate arrays; pipeline processing; public key cryptography; reconfigurable architectures; FPGA implementation; GF(2m) fields; VLSI implementation; Virtex-4; XC4VLX200 FPGA; Xilinx ISE 11; binary finite fields; elliptic curve cryptosystems; high-speed low-cost combinational logic circuits; high-speed pipelined finite field bit-parallel multiplier; one clock cycle; parallel structure; pipelining technique; Clocks; Delays; Elliptic curve cryptography; Galois fields; Gaussian processes; Logic gates; Polynomials; bit-parallel multiplier; elliptic curve cryptography; finite field; pipelining;
Conference_Titel :
Information Security and Cryptology (ISCISC), 2014 11th International ISC Conference on
Conference_Location :
Tehran
DOI :
10.1109/ISCISC.2014.6994015
