A placement strategy for reducing the effects of multiple faults in digital circuits

This paper proposes a fault-aware placement strategy for digital circuits. Placement algorithms usually have a goal of reducing the overall chip area and routing wirelength while the solution proposed in this paper focuses on reducing the effects of multiple faults caused by transients. The target circuits are properly analysed in order to identify scenarios that promote reductions in the overall error rate. The occurrence of these scenarios is then maximised when the proposed placement strategy is executed. Results show that substantial error rate reductions can be achieved.