Title :
Cost-efficient of a cluster in a mesh SRAM-based FPGA
Author :
Rehman, Saif Ur ; Benabdenbi, Mounir ; Anghel, Lorena
Author_Institution :
TIMA Lab., Grenoble Alpes Univ., Grenoble, France
Abstract :
This paper presents a cost-efficient Built-In Self-Test (BIST) scheme for fault detection and diagnosis of a cluster in a mesh FPGA. In this scheme, test cost reduction is achieved by simultaneous testing of logic and intra-cluster interconnect resources without degradation of diagnostic resolution. We analyze the impact of cluster size variation on the testability of a given cluster. Efficiency of this scheme is calculated in terms of the number of test configurations and the corresponding fault coverage for different cluster sizes. Moreover, automated tools developed for BIST implementation are integrated into the standard design flow for bitstream generation. Experimental results show that 100% stuck-at fault coverage can be obtained for a cluster with a gate level diagnostic resolution.
Keywords :
SRAM chips; built-in self test; cost reduction; fault diagnosis; field programmable gate arrays; integrated circuit testing; integrated logic circuits; logic testing; BIST scheme; bitstream generation; cluster size variation; cost-efficient built-in self-test scheme; fault detection; fault diagnosis; gate level diagnostic resolution; intra-cluster interconnect resources; mesh SRAM-based FPGA; simultaneous logic testing; standard design flow; stuck-at fault coverage; test cost reduction; Decision support systems; Erbium; Testing;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International
Conference_Location :
Platja d´Aro, Girona
DOI :
10.1109/IOLTS.2014.6873675
