Early assessment of SEU sensitivity through untestable fault identification

Modern digital circuits are, with each technological evolution, increasingly affected by Single Event Upsets (SEUs). In this paper we propose a static analysis approach for the estimation of the SEU sensitivity of the system under design by identifying untestable faults. The approach relies on a formal specification language to model circuits at the gate-level and on the Linear Temporal Logic (LTL) to express untestability properties that are then evaluated using a model-checking tool. The proposed approach can be applied early during the design process, since it can be individually applied to sub-systems as soon as they are designed, before the whole system is implemented and since it does not require a specific workload to be defined. The approach has been implemented and applied to a set of circuits from the ITC99 benchmark and has been validated against fault injection experiments.