DocumentCode :
1778202
Title :
FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs
Author :
Axelos, N. ; Eftaxiopoulos, N. ; Zervakis, G. ; Tsoumanis, K. ; Pekmestzi, K.
Author_Institution :
Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece
fYear :
2014
fDate :
7-9 July 2014
Firstpage :
200
Lastpage :
201
Abstract :
In this paper we present FF-DICE (Footless-FinFET-DICE), an 8T footless storage element that exhibits soft error resilience characteristics to Single Event Upsets. The proposed cell utilises IDG (Independent Dual Gate) FinFETs to merge the functions of a typical cell´s NMOS drivers and NMOS access transistors, thereby saving 33% of the transistors required for a typical DICE cell. Given the IDG FinFET dual gate mutual coupling and excellent control over the transistor conductive channel, simulations show that the proposed cell can operate as a regular memory cell, with Static Voltage Noise Margin of 341mV, Static Current Noise Margin of 15uA and provides soft-error immunity to particle strikes on single nodes, as well as considerable area savings compared to similar designs.
Keywords :
MOSFET; driver circuits; radiation hardening (electronics); silicon-on-insulator; storage management chips; 8T footless storage element; 8T soft-error tolerant cell; FF-DICE; IDG FinFET dual gate mutual coupling; NMOS access transistors; NMOS drivers; footless-FinFET-DICE; independent dual gate SOI FinFET; particle strikes; regular memory cell; single event upsets; soft error resilience characteristics; soft-error immunity; static current noise margin; static voltage noise margin; transistor conductive channel; voltage 341 mV; Europe; FinFETs; Logic gates; Noise; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International
Conference_Location :
Platja d´Aro, Girona
Type :
conf
DOI :
10.1109/IOLTS.2014.6873696
Filename :
6873696
Link To Document :
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