Cartesian genetic algorithm for boolean synthesis with power consumption restriction

The use of evolutionary algorithms in the boolean synthesis is an interesting technique to generate hardware structures with multiple restrictions. However, one characteristic of these algorithms is their high computational load. This paper presents the implementation of a parallel cartesian genetic programming (CGP) for boolean synthesis on a FPGA-CPU based platform. Power consumption and critical path restrictions were included into the algorithm in order to generate structures to solve any problem. As results a 2-bit comparator is presented, as well as response time and data transitions probability.