A compact and power-efficient CMOS battery charger for implantable devices

A compact and accurate CMOS charger that exhibits a smooth passage from constant-current (CC) to constant-voltage (CV) regulation loops is introduced. Since both CC- and CV-modes are performed with a sole power-FET, area-efficiency is achieved. The loops also share a unity-gain driving stage at the output of respective error amplifiers. The feedback path through this output stage is determined by a continuous transition of an analog signal, so that no sharp commutation between CC and CV loops takes place, preventing the battery from overcharging. The circuit is oriented for Li-ion batteries in implanted devices and its concept has been gauged by a set of PSPICE simulations based on 0.35μm CMOS process parameters. The dual-loop system exhibits inherent stability when driving the battery impedance. Considering a 350mAh cell, the circuit delivers constant currents of 35mA and 350mA, through a 250mΩ-power FET. Upon CV-mode, the battery voltage is accurately regulated to 4.104V, with σ = 1.23mV. End of charge (EoC) is detected when the battery current falls to 17.5mA. The charger works from a 4.4V supply, with overall power efficiency of 68.9% and 93.1%, at beginning and end of CC-region, respectively. A deep-depleted cell is fully charged within 2h.