Performance and impact of process variations in Tunnel-FET ultra-low voltage digital circuits

In this paper, the potential of Tunnel FETs (TFETs) for ultra-low power operation is investigated in the context of digital circuits operating below 500 mV. A comparative analysis of TFETs and SOI CMOS in 32 nm technology is performed through device-and circuit-level simulations, based on a unitary simulation framework where all devices are fairly designed for the same (low) voltage range and the same device-level targets. The performance is evaluated through figures of merit at device and circuit level, quantifying the impact of each device parameter on the performance. The analysis considers both the nominal corner and the impact of the variations of various device parameters, which is evaluated through sensitivity analysis. The results permit to identify the most critical TFET parameters subject to variations that require finer control at process level, to keep circuit-level variations within reasonable bounds. From the perspective of technology scaling, the analysis shows that TFETs can significantly relax the physical-level constraints on gate pitch, thereby mitigating the printability issues in 32-nm technologies and beyond.