A real-time 5-views HD 1080p architecture for 3D-HEVC Depth Modeling Mode 4

The 3D video coding increases significantly the complexity of the coding process when compared to 2D video coding. The emergent 3D-High Efficiency Video Coding (3D-HEVC) standard, which is an extension of the High Efficiency Video Coding (HEVC) standard, inserts new tools in the coding process to better deal with 3D video characteristics. This increase in complexity poses new challenges to attend real-time applications constrains, mainly in software solutions, and thus hardware acceleration is necessary to achieve the performance and energy requirements. This paper presents a hardware architecture for the Depth Modeling Mode (DMM) 4 of the 3D-HEVC emergent standard. The designed architecture is capable to encode all available block sizes in parallel by compounding results of smaller blocks into bigger ones. The architecture was divided in two steps: the Texture Average Calculator and the Contour Computation Step, working in a macro pipeline fashion. The proposed architecture was synthesized for an Altera Stratix V FPGA and is capable to process up to six HD 1080p views in real time.