Deriving reduced transistor count circuits from AIGs

This paper introduces a methodology to reduce transistor count in circuits mapped using simple gates. The resulting circuits are obtained by combining state-of-the-art optimization tools to minimize the number of nodes in and-inverter graph (AIG) representations, with graph-based algorithms to minimize inverters, efficiently modified to reduce transistor count. This work provides reduced transistor count simple gate implementations that can be adopted as fair reference start-points in further investigations, as they are far more efficient than previously published results using simple gates.