Hardware/software debugging of large scale many-core architectures

The size of current multi-processor system-on-chip (MPSoC) is growing unsustainable. Besides, new decentralized software approaches are being developed to handle the management of increasing resources. To verify the system functionality of these novel hardware/software systems, sufficiently accurate models are required. However, current simulation tools have limited scalability and performance; hence hardware prototypes and debugging concepts are necessary for system verification. We present a novel debug approach which offers visualization of hardware/software interaction for system level verification. The debug concept comprises debug probes within each router of the network as well as monitoring units to trace the activity of each core in the MPSoC. In addition a transactor based method is proposed to transmit the huge amount of debug information out of the hardware prototype to evaluate the information on a standard host computer. Experimental results show that the resource overhead is insignificant in contrast to the gain of extensive debug possibilities. Furthermore the number of pins required for the presented debugging concept is kept constant independent of the architecture size and thus we are not facing problems of limited debug interfaces or pins. In comparison to conventional debugging we show improvements in scalability and bandwidth.