Title :
Scalable and high performance HPC architecture with optical interconnects
Author :
Zheng Cao ; Proietti, Roberto ; Yoo, S.J.B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA
Abstract :
We propose a HPC architecture that overcomes I/O limitations by exploiting silicon photonics and optical backplanes with WDM wavelength routing. Compared with fat-tree, 2.5 times throughput with 20% less global switches and cables is achieved.
Keywords :
elemental semiconductors; integrated optics; optical backplanes; optical computing; silicon; HPC architecture; I/O limitations; Si; WDM wavelength routing; cables; global switches; optical backplanes; optical interconnects; silicon photonics; Backplanes; Computer architecture; Optical fibers; Optical interconnections; Optical switches; Relays;
Conference_Titel :
Photonics Conference (IPC), 2014 IEEE
Conference_Location :
San Diego, CA
DOI :
10.1109/IPCon.2014.6995307
