Facet engineering for SiGe/Si stressors in advanced CMOS technology

A two-layer SiGe stressor was introduced for our CMOS technology containing a layer with high Ge content to induce more stress to the channel and on top a layer with lower Ge content for better silicidation [1]. The SiGe is grown undoped prior to the transistor implants to give optimal control of the dopant profile while keeping SiGe close to the gate [2]. However, the silicidation became more critical for more advanced technology node. A very high number of defects were found after silicidation of the SiGe top layer causing severe contact punch through. It was not feasible to achieve the required quality of the silicide using a SiGe cap.