Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers

This paper presents the VLSI design of an energy-efficient, high-throughput soft-input soft-output signal detector for iterative multiple-input multiple-output (MIMO) receiver. The detector is evolved from our previously developed imbalanced fixed complexity sphere decoder and adopts several new algorithm-level techniques to exploit the available a priori information of transmitted bits. More specifically, an adaptive tree-travel control scheme, a reliability-dependent log-likelihood ratio correction method and an iteration-based hybrid node enumeration technique are proposed to provide near-optimal detection performance with much reduced computational complexity. A multi-stage parallel VLSI architecture is developed to implement the proposed algorithm with high detection throughput. Furthermore, the block-level clock gating is deployed to save power when the tree-search space is reduced, while still preserving the constant-throughput feature. As a proof of concept, we designed the iterative detector using a 65-nm CMOS technology and conducted post-layout simulation. The core area is 0.64 mm ² with 198.2 k gates. Working at 240-MHz clock frequency with 1.0-V voltage supply, the detector achieves a maximum 1.44-Gbps throughput. Under frequency-selective channels, the detector core consumes 98.5-, 127.9-, and 149.5-pJ energy per bit detection in open-loop, 2-iteration, and 4-iteration modes, respectively.