Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications

In this paper, a new adaptive computing fabric (ACF) that achieves both real-time multi-mode/multi-rate adaptation and lower error floor for cognitive SoC applications is presented. The VLSI architecture of the ACF is experimentally shown to meet the DVB, 802.3an and 802.ad target specifications. Our design delivers a 10-14 bit error rate (BER) with a bit energyto- noise density of Eb/N0=5dB with an energy-efficiency of 0.61pJ/bit. Experiments are conducted comparing Low-Density Parity-Check (LDPC) codes error correction performance in the presence of unreliable circuits due to aggressive manufacturing defect rates and/or run-time defect rates from components enabled by SoC integration. We report on a 201.6Gbps 65nm CMOS design and Xilinx FPGA prototype, which demonstrates in hardware how real-time adaptive techniques can accelerate decoding convergence and lower the error floor. Finally, We show experimentally that our ACF design can achieve energyefficiency throughput speed-ups at scale in the range of 200x to 5000x as compared to the same algorithm running in software (optimized C program) on a single CPU core.