Title :
A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation
Author :
Venkatasubramanian, Muralidharan ; Agrawal, Vishwani D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
Abstract :
It has been mathematically shown that the testing problem is NP complete. Numerous attempts have been made in creating and designing algorithms to successfully test a digital circuit for all faults in computational linear time. However, due to the complexity of the NP problem, all these attempts start becoming exponential with an increase in circuit size and complexity. Algorithms have been proposed where successful vectors have been used to search for more test vectors with similar properties. However, this leads to a bottleneck when trying to find hard to find stuck-at faults which have only one or two unique tests and their properties may not match other previously successful tests. We propose a new probability based algorithm where new test vectors are generated based on the input probability correlation of previously unsuccessful test vectors. By looking at the correlation between the primary inputs for previously generated test vectors, we use the probability information of 1´s or 0´s at a primary input with respect to other inputs to skew the search in the test vector space. We have shown test time improvements for a 10 input AND gate, c17 and c432 benchmark circuits. We have also shown improvements when comparing our algorithm with a random test generator and weighted-random test generator.
Keywords :
automatic test pattern generation; computational complexity; logic circuits; logic gates; logic testing; probability; search problems; AND gate; NP complete problem; benchmark circuits; circuit size; computational linear time; digital circuit testing; input probability correlation; probability based algorithm; random test generator; single stuck-at fault; test vector search algorithm; testing problem; weighted-random test generator; Algorithm design and analysis; Circuit faults; Computers; Correlation; Generators; Probabilistic logic; Vectors; Probabilistic correlation; test pattern generator; quantum algorithms; unsuccessful test vectors;
Conference_Titel :
Test Workshop (NATW), 2014 IEEE 23rd North Atlantic
Conference_Location :
Johnson City, NY
Print_ISBN :
978-1-4799-5134-5
DOI :
10.1109/NATW.2014.20