System level evaluation of optical RAM circuits based on cross coupled SOAs and SOA-MZIs in the time and frequency domain

One of the key issues in Central Processing Unit (CPU) chips is the “Memory Wall” problem, where the clock frequency of RAM circuits cannot keep up in pace with the clock of the multiple cores. The current approach by chip architects to tackle this obstacle is to increase constantly the size of the cache memories on the dye in order to prevent the cores standing in idle state, while expecting data from the RAM circuit. However, this solution is totally inefficient considering that the dye area of the chip is very precious and could be used alternative for the integration of additional cores, transceivers etc. that would radically enhance the performance of current CPUs. A disruptive solution for data storage within the chip is the introduction of optics in the processor layout by embedding photonic RAM circuits operating at multiple tens of GHz frequencies that would unleash the processing performance of CPU cores at high clock rates. In this direction we present a system level tool for the calculation of maximum obtainable speed from optical RAM cell layouts comprising of three cross coupled switches based on Semiconductor Optical Amplifiers (SOAs) or SOA based Mach-Zehnder interferometers. The investigation is based on a qualitative frequency and a quantitative time domain analysis.