Title :
Optimization of a reliable Network on Chip dedicated to partial reconfiguration
Author :
Tanougast, Camel ; Killian, Cedric
Author_Institution :
LCOMS, Univ. of Lorraine, Metz, France
Abstract :
We present an optimization of reliable Network on Chip (NoC) structure dedicated to dynamic reconfigurable systems (DRS) based on FPGA. The originality of our approach is based on a strategic placement of router incorporating elements of dependability. The solution is a factorization of these reliable routers encompassing routers without any error detection block. This ensures the global reliability of the network and reduce the cost of area, the latency of the data packets and the power consumption. The proposed approach can be applied to the majority NoC topologies.
Keywords :
field programmable gate arrays; integrated circuit reliability; network routing; network topology; network-on-chip; optimisation; DRS; FPGA; NoC structure; NoC topology; data packet latency; dynamic reconfigurable systems; network on chip; network reliability; partial reconfiguration; power consumption; reliable routers; Fault tolerance; Field programmable gate arrays; Heuristic algorithms; Optimization; Routing; Topology;
Conference_Titel :
Control, Decision and Information Technologies (CoDIT), 2014 International Conference on
Conference_Location :
Metz
DOI :
10.1109/CoDIT.2014.6996996
