DocumentCode :
1781823
Title :
Optimized and Dependable Router suitable for dynamic Networks on Chip
Author :
Frihi, M. ; Boutalbi, M. ; Toumi, Salah ; Tanougast, Camel ; Heil, M.
Author_Institution :
LERICA, Univ. of Badji-Mokhtar, Annaba, Algeria
fYear :
2014
fDate :
3-5 Nov. 2014
Firstpage :
783
Lastpage :
788
Abstract :
This paper proposes an optimize dependable router suitable for accurate online error detections in adaptive or dynamic Networks on Chip (NoC). The proposed router detects and localizes data packet errors in the networks based on adaptive routing algorithm. The main originality of the proposed router is its capability to distinguish temporary and permanently errors through specific error detection mechanisms. In this paper, the proposed and interconnected dependable switches are detailed while showing the feasibility and efficiency thanks to simulations online detection cases, and performance evaluations through Virtex VI FPGA implementation.
Keywords :
circuit optimisation; electronic engineering computing; error detection; field programmable gate arrays; integrated circuit testing; network routing; network-on-chip; switches; NoC; Virtex VI FPGA implementation; adaptive routing algorithm; data packet errors; error detection mechanisms; field programmable gate arrays; interconnected dependable switches; networks on chip; online error detections; router; Field programmable gate arrays; Heuristic algorithms; Ports (Computers); Registers; Reliability; Routing; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Control, Decision and Information Technologies (CoDIT), 2014 International Conference on
Conference_Location :
Metz
Type :
conf
DOI :
10.1109/CoDIT.2014.6996997
Filename :
6996997
Link To Document :
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