Measuring the impact of voltage scaling for soft errors in SRAM-based FPGAs from a designer perspective

The susceptibility of SRAM-based FPGAs to soft errors increases with each technology node due to the reduction of transistor size, the reduction of voltage supply and the increase of density of devices. This work presents the actual impact of voltage reductions for neutron-induced soft errors in SRAM-based FPGAs. We run neutron radiation experiments with a Spartan-6 (45nm) FPGA at different supply voltages to measure the soft error susceptibility. We measure the variation of the susceptibility of the device (static test) and also of a functional system implemented in it (dynamic test). Experimental results show that 8% reduction in the VDD supply voltage can result in 30% higher device susceptibility. When this is translated to a functional system implemented in the FPGA, the system error rate can have a variation of 55% for a voltage variation of 19%, which has to be taken into account by the designer of the system.