Integrated cross-layer solutions for enabling silicon photonics into future chip multiprocessors

Nanophotonic is a promising solution for interconnections in future chip multiprocessors (CMPs) due to its intrinsic low-latency and low-power features. This paper proposes an integrated approach with physical level design choices to select the most suitable optical network topology, and an adhoc software strategy to improve performance and reduce energy consumption of a tiled CMP architecture. We adopt an all-optical reconfigurable network which has been designed to significantly reduce path-setup latency and energy consumption. Specifically the optimization aims at distributing the traffic into the Network on Chip (NoC) in such a way to limit resurce usage conflicts (during path-setups) and have a more uniform utilization of the fast optical resources. On-chip photonics indeed is the key enabler for such a strategy permitting to reach even far destinations with a reduced latency, the same as the closest ones. We investigate performance/power consumption effects on a CMP system and we compare against both a high-performance electronic folded Torus NoC and the standard optical reconfigurable architecture. The optical network improves 7% on average over the electronic counterpart and, especially when using the dedicated software optimization for matching application locality and network features, it reaches about 26% average execution time improvement.