A 2.2–2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop using 65 nm CMOS process

A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop (PLL) using 65 nm CMOS process is presented in this paper. A delay-locked loop is employed in the proposed PLL to automatically align the phase difference between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator. At 2.3 GHz, the measured phase noises at 1 kHz, 10 kHz, 100 kHz, and 1 MHz offset are better than -110, -112, -122 and -128.4 dBc/Hz, respectively, with an rms jitter of 228 fs. This work demonstrates low phase noise, low jitter, and good robustness over frequency and temperature variations.