Design and measurement of 500-MS/s ΣΔ modulator with half-delayed return-to-zero feedback DAC

A second-order continuous-time (CT) low-pass ΣΔ modulator using a single feedback digital-to-analog converter (DAC) is presented. To reduce the feedback DACs by one, we introduce half-delayed return-to-zero (HRZ) feedback signaling and feed-forward topology. The HRZ feedback scheme reduces power consumption and die area by removing a summing amplifier and DAC for the excess-loop delay compensation and the feed-forward topology saves additional power and area by replacing the feedback DAC with feed-forward path. The concept is implemented in a 500 MS/s CT ΣΔ modulator for 12-MHz signal bandwidth in a 130 nm CMOS process which occupies 0.19 mm². The Measurements show that the modulator achieves spurious free dynamic range of 61.2 dB, signal-to-noise and distortion ratio of 52.5 dB, and dynamic range of 55 dB. The modulator consumes 9.96 mW at a 1.2 V supply.