An FPGA-Based Design of Efficient QKD Sifting Module

Quantum Key Distribution (QKD) technique has drawn many attentions because it can generate and distribute cryptographic keys with provable information theoretic security. To achieve a high secure key rate, it is a developing trend to adopt the FPGA-based scheme. Sifting is an important processing module of QKD post processing system (QKDPPS) and its communication traffic and input data rate are much larger than other modules of QKDPPS. In this paper, a FPGA-based design of efficient QKD sifting module is presented. To reduce the interaction data amount and thus increase the secure key rate, a high compression ratio round-length based compression encoder and decoder are designed in the sifting modules of two parties. To accelerate the processing speed and thus increase the secure key rate, parallelized processing scheme is designed. The experimental results demonstrate the feasibility and efficiency of the sifting module.