Low-power and high-performance 5:2 compressors

Compressors play a significant role in overall performance of multipliers and hence in efficiency of arithmetic circuits. To further improvement of multipliers higher order compressors have been considered. In this paper, two novel 5:2 compressors are presented. The proposed architectures lay emphasis on the idea of making the carry-out signal C_out2 independent of C_in1. Therefore, we have developed our designs to limit the carry propagation to one compressor, thereby reducing the overall propagation delay. In addition, in some compressor designs, one or more full-adder (FA)-equivalent building block(s) can be found. Using a particular CMOS FA in our design, we have introduced a more optimized architecture. The proposed architectures are compared with the best architectures presented in the literature in terms of power, delay and area. Simulations have been conducted by HSPICE software at 90nm technology. Simulation results of the proposed architectures show up to 30% improvement in Power-Delay Product (PDP) for the supply voltage of 1V and ambient temperature of 25°C.