Design and evaluation of low power and high speed logic circuit based on the modified gate diffusion input (m-GDI) technique in 32nm CNTFET technology

Author

Abiri, Ebrahim ; Salehi, Mohammad Reza ; Darabi, Abdolreza

Author_Institution

Dept. of Electr. & Electron. Eng., Shiraz Univ. of Technol., Shiraz, Iran

fYear

2014

fDate

20-22 May 2014

Firstpage

67

Lastpage

72

Abstract

Speed, power and chip area are the crucial parameters in logic circuit designs. With the gate diffusion input (GDI) technique, low power logic gates can be designed with the minimum number of transistors. In this paper the modified GDI (m-GDI) cell based on the basic GDI cell is proposed for designing the logic circuits in nano process. In the proposed GDI cell, the chip area for the pull up and pull down networks are reduced about 80% and 50%, respectively, in comparison with the basic GDI cell. Also power delay production (PDP) has improved in this design. The simulation is done in 32nm technology with H-SPICE software under the condition of 0.9V supply voltage, and 500MHz frequency.

Keywords

SPICE; field effect transistors; high-speed integrated circuits; logic circuits; logic design; logic gates; low-power electronics; CNTFET technology; H-SPICE software; frequency 500 MHz; high speed logic circuit; low power logic circuit; low power logic gates; modified gate diffusion input technique; power delay production; size 32 nm; voltage 0.9 V; CNTFETs; Inverters; Logic gates; MOSFET; Multiplexing; Threshold voltage; DTMOSFET technique; GDI technique; Logic gates; Low power; Multiplexer; PDP;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2014 22nd Iranian Conference on

Conference_Location

Tehran

Type

conf

DOI

10.1109/IranianCEE.2014.6999505

Filename

6999505