New all digital frequency divider and phase shifter

In this paper, a counter based all digital frequency divider is presented. The architecture is based on a counter and a control logic which controls the division ratio. Depending on the control logic circuitry, phase shifting of divided clock signal is also possible. By utilizing both divided signal and shifted signal, fractional ratios are implemented. Phase shifting relies on division factor. Key circuit of the architecture is counter that consumes more power than control logic. Depending on circuitry of the counter, power consumption could be optimized. Multiple division ratios are possible to be implemented by utilizing an appropriate control structure. The circuits were simulated in standard TSMC 0.18 um CMOS technology with nominal power supply of 1.8v.