Title :
High speed domino logic circuit for improved performance
Author :
Shiksha ; Kashyap, Kamal K.
Author_Institution :
Sch. of VLSI Design & Technol., NIT, Kurukshetra, India
Abstract :
Dynamic logic style is used in high performance circuit designs due to its high speed. But during cascading of dynamic gates, problem arises due to charge sharing, charge redistribution and charge leakage. To avoid these problems, domino logic design is used in the circuit due to their advantages such as their high speed and less noise immunity. In this paper we have proposed a new domino circuit which has very small speed power product as compared to previous designs of domino logic circuits. Simulation are carried out for 90 nm technology with Vdd= 1 Volt, for the case of OR gate.
Keywords :
MOSFET; high-speed integrated circuits; logic design; logic gates; NMOS transistors; OR gate; high performance circuit designs; high speed domino logic circuit; size 90 nm; CMOS integrated circuits; Delays; Logic circuits; Logic gates; Noise; Threshold voltage; Transistors; Dynamic gates; evaluation phase; pre-charge phase and robustness;
Conference_Titel :
Engineering and Systems (SCES), 2014 Students Conference on
Conference_Location :
Allahabad
Print_ISBN :
978-1-4799-4940-3
DOI :
10.1109/SCES.2014.6880112
