6×6 booth multiplier implemented in modified split-path data driven dynamic logic

Split-path data driven dynamic logic (SPD³L) is used wherever low power design is desired. It uses subset of input signals instead of global clock to maintain the correct pre-charge and evaluation phases. Elimination of clock network results in substantial reduction in power dissipation compared to dynamic domino logic. In this work, two 6×6 booth multipliers are implemented in 1.8V 0.18um CMOS technology, with one in normal `SPD<sup>3</sup>L´ and the other using the proposed i.e. `Modified SPD³L´. Depending on the input patterns, the proposed technique saves 8 to 16% power and is slightly faster than SPD³L. Simulations and designs are performed on Cadence Virtuoso and Spectre tools using UMC 0.18um technology.