Design of ultra-low-power CMOS amplifiers based on flicker noise reduction

Author

Akbari, Mohammad ; Biabanifard, Sadegh ; Hashemipour, Omid

Author_Institution

Microelectron. Lab., Shahid Beheshti Univ., Tehran, Iran

fYear

2014

fDate

20-22 May 2014

Firstpage

403

Lastpage

406

Abstract

In this paper, a weak inversion technique for recycling folded cascode (RFC) and folded cascode (FC) operational amplifier design with flicker noise reduction is presented. Flicker noise is the dominant noise source in silicon MOSFET´s especially in low frequency. A new formulation for input referred flicker noise in weak inversion region is also presented and an efficient tradeoff between input refereed flicker noise power and frequency response is performed for optimum design in weak inversion region. This procedure will be useful for all of CMOS weak inversion amplifiers. The proposed technique significantly enhances the conventional noise performance of FC and RFC amplifier. The theoretical analysis is verified in 0.18 μm CMOS technology.

Keywords

CMOS analogue integrated circuits; frequency response; low-power electronics; operational amplifiers; flicker noise reduction; frequency response; input refereed flicker noise power; operational amplifier design; recycling folded cascode amplifier design; silicon MOSFET; size 0.18 mum; ultra-low-power CMOS amplifiers; weak inversion technique; 1f noise; CMOS integrated circuits; Frequency response; MOSFET; Transconductance; CMOS amplifier; flicker noise; folded cascode; low power; weak inversion;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2014 22nd Iranian Conference on

Conference_Location

Tehran

Type

conf

DOI

10.1109/IranianCEE.2014.6999573

Filename

6999573