High efficiency class E power amplifier with drain source merging technique

This paper studies the effects of different cell-based layout styles of cascode class-E power amplifiers (PAs) in 0.18-μm TSMC CMOS technology. Different types of layouts for PA cascode transistors are investigated. Merging technique for the PA cascode transistors is introduced that reduces the auxiliary shunt capacitors of cascode transistors. As a result, total power dissipation of class E PA is reduced and its efficiency is improved. To demonstrate it applicability, the design of a state-of-the-art 1.8-GHz differential cascode class E PA is presented. At 23-dBm output power, a power added efficiency (PAE) as high as 33% for the merging technique and 31% for conventional cascode transistors, was obtained from postlayout simulation with 1.8 V supply.