Radix-4 implementation of redundant interleaved modular multiplication on FPGA

Modular multiplier is the most important block in public key cryptography which has a direct effect on the whole cryptosystem. In this paper, an architecture is proposed to perform the well-known interleaved modular multiplier in radix-4. Although this architecture uses a bigger look up table, we reduce the pre-processing time and number of needed clock cycles. Synthesis results show that the proposed method is superior to previous architectures, in terms of the speed, area and area-delay product.