DocumentCode
1785635
Title
Minimization of a reversible quantum 2n-to-n BCD priority encoder
Author
Lisa, Nusrat Jahan ; Babu, Hafiz Md Hasan
Author_Institution
Dept. of Comput. Sci. & Eng., Ahasnaullah Univ. of Sci. & Technol., Dhaka, Bangladesh
fYear
2014
fDate
8-10 July 2014
Firstpage
77
Lastpage
82
Abstract
In this paper, we propose a reversible quantum 2n_ to-n BCD priority encoder circuit, where n is the number of output bits. The proposed design of the 2n-to-n BCD priority encoder circuit shows that it is composed of quantum circuits for OR operation and quantum NOT gates. We present an algorithm to construct a minimized quantum 2n-to-n BCD priority encoder circuit. A technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. Our circuit performs better than the existing ones in terms of quantum gates, delays, garbage outputs, constant inputs, quantum gate calculation complexity, area and power, e.g., the proposed quantum 8-to-3 BCD priority encoder circuit improves 41.25% on the number of quantum gates, 46.05% on delays, 48% on garbage outputs, 60% on constant inputs and 41.25% on area and power than the existing circuit. We also simulate the proposed quantum BCD priority encoder circuit using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
Keywords
binary codes; circuit complexity; delay circuits; logic design; minimisation; quantum gates; Microwind DSCH 2.7; OR operation; delays; minimization; quantum NOT gates; quantum gate calculation complexity; reversible quantum 2n_ to-n BCD priority encoder circuit design; Computer science; Decision support systems; Educational institutions; Handheld computers; Nanoscale devices; Delay; Garbage Output; Quantum Circuit; Quantum Gate; Qubits;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanoscale Architectures (NANOARCH), 2014 IEEE/ACM International Symposium on
Conference_Location
Paris
Type
conf
DOI
10.1109/NANOARCH.2014.6880474
Filename
6880474
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