• DocumentCode
    1785690
  • Title

    A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures

  • Author

    Goudarzi, Arman ; Lakin, Matthew R. ; Stefanovic, Darko ; Teuscher, Christof

  • Author_Institution
    Dept. of Comput. Sci., Univ. of New Mexico, Albuquerque, NM, USA
  • fYear
    2014
  • fDate
    8-10 July 2014
  • Firstpage
    116
  • Lastpage
    121
  • Abstract
    Reconfiguration has been used for both defect- and fault-tolerant nanoscale architectures with regular structure. Recent advances in self-assembled nanowires have opened doors to a new class of electronic devices with irregular structure. For such devices, reservoir computing has been shown to be a viable approach to implement computation. This approach exploits the dynamical properties of a system rather than specifics of its structure. Here, we extend a model of reservoir computing, called the echo state network, to reflect more realistic aspects of self-assembled nanowire networks. As a proof of concept, we use echo state networks to implement basic building blocks of digital computing: AND, OR, and XOR gates, and 2-bit adder and multiplier circuits. We show that the system can operate perfectly in the presence of variations five orders of magnitude higher than ITRS´s 2005 target, 6%, and achieves success rates 6 times higher than related approaches at half the cost. We also describe an adaptive algorithm that can detect faults in the system and reconfigure it to resume perfect operational condition.
  • Keywords
    adders; fault diagnosis; logic gates; multiplying circuits; nanowires; self-assembly; AND gate; ITRS 2005 target; OR gate; XOR gate; adder; defect-tolerant nanoscale architecture; digital computing; echo state network; electronic device; fault detection; fault-tolerant digital logic; fault-tolerant nanoscale architecture; multiplier circuit; reservoir computing; self-assembled nanowire architecture; variation-tolerant digital logic; word length 2 bit; Computational modeling; Computer architecture; Nanoscale devices; Reservoirs; Self-assembly; Training; Transfer functions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanoscale Architectures (NANOARCH), 2014 IEEE/ACM International Symposium on
  • Conference_Location
    Paris
  • Type

    conf

  • DOI
    10.1109/NANOARCH.2014.6880504
  • Filename
    6880504