DocumentCode
1785693
Title
A fast design space exploration for VLIW architectures
Author
Yazdani, Reza ; Sheidaeian, Hamed ; Salehi, Mostafa E.
Author_Institution
Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
fYear
2014
fDate
20-22 May 2014
Firstpage
856
Lastpage
861
Abstract
Design space exploration is referred to a search on possible architecture configurations of a system, to find the feasible and optimum solution for the desired application based on the defined objectives. The objective could be optimization of performance, power or area of the system. There are various numbers of algorithmic approaches for exploration. This paper presents a novel method for design space exploration on VLIW processors. Our proposed approach is mainly based on space pruning methodology using binary search tree. This method will be experimented on a specific VLIW embedded system. The focus of the exploration is on optimizing performance or area of the base architecture through finding the optimum number of resources and cache sizes. Experimental results proves that our algorithm gets to the optimum solution comparing with the solution resulted by exhaustive approach, and also outperforms this approach through a logarithmic order against a polynomial one.
Keywords
cache storage; embedded systems; multiprocessing systems; optimisation; parallel architectures; tree searching; VLIW architectures; VLIW embedded system; VLIW processors; architecture configurations; base architecture; binary search tree; cache sizes; design space exploration; optimizing performance; space pruning methodology; Algorithm design and analysis; Computer architecture; Optimization; Program processors; Registers; Space exploration; VLIW; Binary Search Pruning; Design Space Exploration (DSE); VLIW architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Engineering (ICEE), 2014 22nd Iranian Conference on
Conference_Location
Tehran
Type
conf
DOI
10.1109/IranianCEE.2014.6999656
Filename
6999656
Link To Document