Title :
A spare link based reliable Network-on-Chip design
Author :
Chatterjee, Niladrish ; Prasad, Narayan ; Chattapadhya, Santanu
Author_Institution :
Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, Kharagpur, India
Abstract :
In this paper we have presented a reliable On-chip interconnection network design using spare links. It helps to mitigate the problem of fault chain formation due to failure of boundary links. The modified router design uses the redundant ports in boundary routers along with spare links for establishing connection with adjacent routers in case of link faults. This design modification on mesh based network along with proposed routing algorithm improves system reliability in case of single and multiple link failures. The performance evaluation in terms of network latency has also been improved compared to recent works with minimal area overhead.
Keywords :
failure analysis; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; network-on-chip; adjacent routers; boundary link failure; boundary router algorithm; design modification; fault chain formation problem; mesh based network; minimal area overhead; modified router design; multiple link failures; network latency; redundant ports; reliable on-chip interconnection network design; spare link based reliable network-on-chip design; system reliability; Circuit faults; Fault tolerance; Fault tolerant systems; Ports (Computers); Registers; Routing; Fault tolerant Routing; Network-on-Chip; Reliability; Spare Link;
Conference_Titel :
VLSI Design and Test, 18th International Symposium on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-5088-1
DOI :
10.1109/ISVDAT.2014.6881036
