Title :
A locally reconfigurable Network-on-Chip architecture and application mapping onto it
Author :
Soumya, J. ; Sharma, Ashok ; Chattopadhyay, Subrata
Author_Institution :
Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
Abstract :
This paper presents a reconfigurable Network-on-Chip (NoC) architecture built around mesh topology. It provides the facility of changing the attachment of cores to local routers across applications. Applications share cores, but communication pattern between them may vary. Compared to many other reconfigurable NoCs, our architecture needs only about 0.2% extra area overhead than simple mesh. Application mapping and reconfiguration policy have been developed using Integer Linear Programming (ILP) and heuristic for the proposed topology. It has been shown that the reconfiguration strategy could improve communication costs of applications significantly which often resulted in improved latency and energy values, keeping throughput unaffected.
Keywords :
circuit optimisation; heuristic programming; integer programming; linear programming; network-on-chip; reconfigurable architectures; ILP; application mapping; communication costs; communication pattern; heuristic; integer linear programming; local routers; locally reconfigurable network-on-chip architecture; mesh topology; reconfigurable NoCs; reconfiguration policy; Benchmark testing; Computer architecture; Integer linear programming; Multiplexing; Network topology; Optimization; Topology; Communication cost; Integer Linear Programming; Reconfiguration;
Conference_Titel :
VLSI Design and Test, 18th International Symposium on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-5088-1
DOI :
10.1109/ISVDAT.2014.6881041