High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications

In this paper, we present the impact of spacer dielectric on a junctionless transistor (JLT) FinFET based circuit/SRAM memory cell. JLT FinFETs with high-k spacers provide excellent electrostatic integrity as well as reduction in short channel effects (SCEs). Fringing electric field through spacer increases effective channel length in the OFF-state, whereas in ON-state it is unaffected. It is observed that the drive current, leakage current, drain induced barrier lowering (DIBL) and sub-threshold swing (SS) are improved. The JLT structure with spacers leads to better noise-margins of CMOS inverter. Moreover, the JLT architecture also improves the performance of SRAM in terms of static-noise margins (SNMs) and leakage power with increase in high-k spacer value. High-k spacer increase the capacitance of the device, so ring oscillator delay and SRAM access times are degraded.