DocumentCode :
1786218
Title :
A re-router for optimizing wire length in two-and four-layer no-dogleg channel routing
Author :
Sau, Swagata Saha ; Pal, Rajat Kumar
Author_Institution :
Dept. of Comput. Sci., Sammilani Mahavidyalaya, Kolkata, India
fYear :
2014
fDate :
16-18 July 2014
Firstpage :
1
Lastpage :
6
Abstract :
In VLSI physical design automation minimization of total (vertical) wire length is one of the most important problems as it reduces the cost of physical wiring required along with the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delays. Since the problem of computing minimum wire length routing solutions in no-dogleg reserved two- and four-layer channel routing is NP-hard, it is interesting to develop heuristic algorithms that compute routing solutions of as minimum total (vertical) wire length as possible. In this paper we develop two algorithms to minimize the total (vertical) wire length in channel routing problem. First we develop an efficient re-router Further_Reduced_Wire_Length (FRWL) to optimize the wire length in the reserved two-layer (VH) no-dogleg channel routing model and then we develop a next algorithm Four_Layer_Reduced_Wire_Length (FLRWL) to optimize the total (vertical) wire length in the reserved four-layer (VHVH) no-dogleg Manhattan routing model. Experimental results computed for available benchmark instances are greatly encouraging.
Keywords :
VLSI; computational complexity; integrated circuit design; integrated circuit modelling; minimisation; network routing; FLRWL algorithm; NP-hard problem; VLSI physical design automation minimization; cost reduction; efficient re-router FRWL; efficient re-router further_reduced_wire_length; electrical hazards; four_layer_reduced_wire_length algorithm; heuristic algorithm; interconnection; minimum wire length routing solutions; physical wiring; power consumption; reserved four-layer no-dogleg Manhattan channel routing model; reserved two-layer no-dogleg channel routing model; signal propagation delays; tolal wire length optimization; vertical wire length minimization; Algorithm design and analysis; Computational modeling; Minimization; Routing; Time complexity; Very large scale integration; Wires; Channel routing problem; Manhattan routing; No-dogleg; Parametric difference; VLSI; Wire length minimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and Test, 18th International Symposium on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-5088-1
Type :
conf
DOI :
10.1109/ISVDAT.2014.6881057
Filename :
6881057
Link To Document :
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